For the Intel486™ and Pentium® processors, the LOCK# signal is always asserted on the bus
during a LOCK operation, even if the area of memory being locked is cached in the processor.
For the P6 family processors, if the area of memory being locked during a LOCK operation is
cached in the processor that is performing the LOCK operation as write-back memory and is
completely contained in a cache line, the processor may not assert the LOCK# signal on the bus.
Instead, it will modify the memory location internally and allow it’s cache coherency mecha-
nism to insure that the operation is carried out atomically. This operation is called “cache
locking.” The cache coherency mechanism automatically prevents two or more processors that
have cached the same area of memory from simultaneously modifying data in that area.
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