#define GPCON(x) __REG2(0x56000000, (x) * 0x10)
# define __REG2(x,y) ( __builtin_constant_p(y) ? (__REG((x) + (y))) : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
(*(volatile u32 *)((u32)&__REG(x) + (y)))
#define __REG(x) __REGP(io_p2v(x))
#define io_p2v(x) ((x) | 0xa0000000)
*
* S3C2410 internal I/O mappings
*
* We have the following mapping:
* phys virt
* 48000000 e8000000
*/
#define VIO_BASE 0xe8000000 /* virtual start of IO space */
#define PIO_START 0x48000000 /* physical start of IO space */
#define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
/*
* This __REG() version gives the same results as the one above, except
* that we are fooling gcc some how so it generates far better and smaller
* assembly code for access to contigous registers. It's a shame that gcc
* doesn't guess this by itself
*/
#include <stdio.h>
typedef unsigned int u32;
typedef struct {
volatile u32 offset[4096];
} __regbase;
#define io_p2v(x) ((x) | 0xa0000000)
#define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
#define __REG(x) __REGP(io_p2v(x))
int main()
{
printf ("%x\n", (u32)&__REG(0x56000004));
return (0);
}
[beyes@localhost s3c2410]$ ./set_gpio.exe
f6000004
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